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In an article recently published in the journal Nature, researchers developed a 300-mm cryogenic probing process to obtain high-volume data on spin qubit devices across full wafers and optimized an industry-compatible process to fabricate spin qubit devices on a low-disorder host material to realize automated probing of single electrons in spin qubit arrays across 300-mm wafers.

Substantial numbers of physical qubits are required to build a fault-tolerant quantum computer. Recently, silicon quantum dot spin qubits/qubits based on silicon electrons have displayed two-qubit and single-qubit fidelities above 99%, satisfying the error correction thresholds.

Integrated spin qubit arrays have currently attained sizes equal to six quantum dots, and bigger quantum dot platforms in two-dimensional (2D) and one-dimensional (1D) configurations have also been demonstrated. However, the number of physical qubits must significantly increase to realize real-world applications using spin qubit technology. Thus, spin qubit devices must be fabricated with uniformity, volume, and density comparable with classical computing chips, which currently consist of billions of transistors.

Fabricating spin qubit devices using a similar infrastructure as classical computing chips can facilitate the development of fault-tolerant quantum computers using the spin qubit technology and unlock the spin qubits' potential for scaling.

This is because spin qubit technology possesses inherent advantages for scaling due to the approximate qubit size of 100 nm and built-in compatibility with modern complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure, specifically in the case of silicon-based devices.

Currently, yield and process variation are the major challenges for spin qubits. Additionally, the cryogenic electrical testing bottleneck hinders the scaling of solid-state quantum technologies like superconducting and topological qubits and spin qubits.Thus, the cryogenic device testing scale must maintain pace with the increasing fabrication complexity to ensure efficient device screening and improve statistical metrics like voltage variation and qubit yield. Yield and process variation in quantum devices can be improved by combining process changes with statistical measurements of indicators like component yield and voltage variation.

In this study, researchers proposed a testing process using a cryogenic 300-mm wafer prober to obtain high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K across full wafers. Additionally, they combined low process variation with a low-disorder host material to optimize an industry-compatible process for spin qubit device fabrication on silicon/silicon-germanium (Si/SiGe) heterostructures.

These proposed advancements were synergistic as the development of the full-wafer cryogenic test capability can enable the complex 300-mm fabrication process optimization and the optimized fabrication process can improve the reliability of the devices, enabling high-fidelity automated measurements across wafers.

Collectively, these advancements culminated in automated single-electron probing in spin qubit arrays across 300-mm wafers. In this work, the spin qubit devices were synthesized in Intel's D1 factory, where the CMOS logic processes are developed. A Si/SiGe heterostructure grown on 300-millimeter silicon wafers was used as the host material.

Researchers selected this structure to exploit the prolonged electron spin coherence in silicon and its applicability for multiple qubit encodings. All patterning was performed using optical lithography. Extreme ultraviolet lithography was employed for quantum dot gate patterning in a single pass.

Additionally, all device sub-components were fabricated using fundamental industry techniques like chemical-mechanical polishing, etching, and deposition. The AEM Afore and Bluefors-manufactured cryo-prober/cryogenic wafer prober used in this work can load and cool 300-millimeter wafers to 1.0 K base temperature at the chuck and 1.6 0.2 K electron temperature. Thousands of test structures and spin qubit arrays on the wafer were measured after cooldown.

Low process variation and high yield were successfully achieved across the 300-mm wafer using the proposed approach. The proposed cryogenic testing method provided fast feedback to enable the CMOS-compatible fabrication process's optimization, resulting in low process variation and high yield.

Using this proposed system, measurements of the spin qubits' operating point were successfully automated and the transitions of single electrons were thoroughly investigated across full wafers. Results obtained by analyzing the random variation in single-electron operating voltages demonstrated that the optimized fabrication process results in low levels of disorder at the 300-mm scale.

The high device yield combined with the cryogenic wafer prober enabled a simple path from device fabrication to the investigation of spin qubits, which eliminated failures due to electrostatics or yield at the dilution refrigerator stage. Overall, an extensible and large unit cell of up to 12 qubits was realized using a high-volume cryogenic testing method, an all CMOS-industry-compatible fabrication process with low process variation, and a low-disorder host material/Si/SiGe.

To summarize, the findings of this study established a new standard for the reliability and scale of spin qubit devices and paved the way for more complex and much larger spin qubit arrays of the future.

Neyens, S., et al. et al. (2024). Probing single electrons across 300-mm spin qubit wafers. Nature, 629(8010), 80-85. https://doi.org/10.1038/s41586-024-07275-6, https://www.nature.com/articles/s41586-024-07275-6

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Advancing Spin Qubit Technology: Cryogenic Probing - AZoQuantum